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Memory architecture
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#	Item
31	Seven at One Stroke: Results from a Cache-Oblivious ∗ Paradigm for Scalable Matrix Algorithms Michael D. Adams David S. Wise Add to Reading List Source URL: michaeldadams.org Language: English - Date: 2012-07-27 19:30:16 Computing Cache Computer hardware Computer memory Computer engineering Central processing unit Computer architecture Numerical software CPU cache Basic Linear Algebra Subprograms Cache-oblivious algorithm Page
32	TayzGrid Command Line Tools Guide June 25, 2015 Table of Contents Add to Reading List Source URL: www.alachisoft.com Language: English - Date: 2015-11-11 09:26:53 Cache Computing Computer architecture Computer memory Computer engineering Forward proxy Reverse proxy AppFabric Caching Draft:Fragment Caching
33	Transactional In-memory Storage for Extended MapReduce Kim-Thomas Rehmann and Michael Schöttner Heinrich-Heine Universität Düsseldorf Abteilung Betriebssysteme Add to Reading List Source URL: www.gsd.inesc-id.pt Language: English - Date: 2012-02-23 13:28:01 Computing Concurrent computing Parallel computing Transaction processing Data management Distributed computing architecture Databases MapReduce Replication Serializability File system Map
34	Cut-Through Delivery in Trapeze: An Exercise in Low-Latency Messaging Kenneth G. Yocum Jeffrey S. Chase Andrew J. Gallatin Add to Reading List Source URL: www.cs.duke.edu Language: English - Date: 1998-06-22 10:13:50 Computing Computer architecture Computer networks Computer networking Computer memory Direct memory access Motherboard Network interface controller Latency Low latency Transmission Control Protocol Cell
35	4stack Processor’s User Manual Bernd Paysan 25th April 2000 2 Add to Reading List Source URL: bernd-paysan.de Language: English - Date: 2000-04-25 15:51:49 Computing Computer architecture Computer engineering Instruction set architectures Computer memory Assembly languages Stack Processor register Endianness Comparison of instruction set architectures 16-bit Pointer
36	DATASHEET - TARGET DA14583 Low Power Bluetooth Smart SoC with Flash memory General description Add to Reading List Source URL: www.dialog-semiconductor.com Language: English - Date: 2015-04-10 06:31:38 Computing Microcontrollers Computer architecture Classes of computers Serial Peripheral Interface Bus Universal asynchronous receiver/transmitter Bluetooth Banana Pi TI MSP430
37	Lecture 34: One-sided Communication in MPI William Gropp www.cs.illinois.edu/~wgropp Thanks to Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2015-04-21 12:42:32 Computing Concurrent computing Software engineering Parallel computing Memory management Distributed computing architecture Computer architecture Shared memory Memory C dynamic memory allocation Message Passing Interface Distributed shared memory
38	NMI: A New Memory Interface to Enable Innovation David Roberts1, Amin Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:30 Computing Computer architecture Computer engineering Computer memory Parallel computing Heterogeneous System Architecture Heterogeneous computing Random-access memory General-purpose computing on graphics processing units
39	¨ FUR ¨ INFORMATIK FAKULTAT ¨ MUNCHEN ¨ DER TECHNISCHEN UNIVERSITAT Add to Reading List Source URL: www5.in.tum.de Language: English - Date: 2014-01-10 07:00:27 Concurrent computing Computing Parallel computing Distributed shared memory Shared memory Distributed memory Memory architecture Multiprocessing Synchronization Cache coherence Cache Symmetric multiprocessing
40	White Paper  Memory Performance of Xeon E5-2600 v4 (Broadwell-EP) based Systems White Paper FUJITSU Server PRIMERGY Memory Performance of Xeon E5-2600 v4 (BroadwellEP) based Systems The Xeon E5-2600 v4 (Broadwell-EP) Add to Reading List Source URL: sp.ts.fujitsu.com Language: English - Date: 2016-04-18 10:55:02 Computer architecture SDRAM Computing Computer hardware Xeon DIMM DDR3 SDRAM Broadwell DDR4 SDRAM Ivy Bridge Haswell DDR SDRAM